FOLCS: A Lightweight Implementation of a Cycle-accurate NoC Simulator on FPGAs

Recent trends toward multi- and many-core architectures make computer architecture simulation time-consuming. Although core counts are increasing, it is difficult to exploit parallelism in simulators because of synchronization overheads. FPGAs are effective tools to reduce simulation time. The size of a circuit implementable on them, however, is limited by the number of block RAMs and slices they have. It is important to develop a lightweight simulator of each processor component so that a full-system simulator as a whole fits into an FPGA. In this paper, we focus on a network-on-chip (NoC), which is an intra-chip communication fabric to connect cores and memory controllers. We present Flit-Oriented Lightweight Cycle-accurate network Simulator (FOLCS) that is a NoC simulator running on an FPGA. FOLCS provides a cycle-accurate NoC model with moderate resource requirements. The accuracy is validated by case studies that compare network latency computed by FOLCS and a reference software simulator. The post place-and-route report shows that FOLCS requires less block RAMs than previous methods.