用于低于0.25 /spl μ m VLSI技术的硅化膜的高电流效应

K. Banerjee, C. Hu, A. Amerasekera, J. Kittl
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引用次数: 12

摘要

本文首次报道了在n/sup +/-Si和n/sup +/多晶硅上形成的TiSi/sub 2/和CoSi/sub 2/薄膜在直流和脉冲应力条件下的大电流传导特性和建模。硅化物的大电流电导率受工艺条件的影响较大。模拟了硅化物薄膜在直流和脉冲大电流应力下的非线性I-V特性,证明了这种非线性是由自加热引起的。与直流和脉冲电流应力相关的两个物理参数B和/spl λ /已被证明能够描述薄膜对大电流传导的灵敏度。在大电流下,观察到硅化结构的电阻突然降低。详细分析了这种阻力下降的演变过程。结果表明,其原因与结构的熔化有关,这也导致了应力后硅化物膜电阻的下降。这些失效的临界电流受到硅化膜宽度和脉冲持续时间的强烈影响。CoSi/ sub2 /薄膜和多晶硅薄膜对大电流传导和降解更敏感。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High current effects in silicide films for sub-0.25 /spl mu/m VLSI technologies
Characterization and modeling of high current conduction in TiSi/sub 2/ and CoSi/sub 2/ films formed on n/sup +/-Si and n/sup +/ poly-Si under DC and pulsed stress conditions is reported for the first time. High current conductance of silicides is shown to be strongly affected by the technology and process conditions. The nonlinear I-V characteristics of silicide films under DC and pulsed high current stress has been modeled and the nonlinearity has been shown to be due to self-heating. Two physical parameters, B and /spl lambda/, associated with DC and pulsed current stress, have been shown to be able to describe the sensitivity of the films to high current conduction. At high currents, an abrupt lowering of the resistance of the silicided structures is observed. Detailed analysis of the evolution of this resistance drop has been made. It is shown that the cause is related to the melting of the structures, which also causes degradation in the post-stress silicide film resistance. The critical current for these failures has been shown to be strongly influenced by the silicide film width and the time duration of the pulse. CoSi/sub 2/ films and films on poly-Si are shown to be more sensitive to high current conduction and degradation.
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