Automating the generation of hardware accelerators from custom arithmetic functions

Field programmable gate arrays (FPGAs) have become the standard for fast prototyping and evaluation of custom IP cores. However, the creation of complex circuits is a time consuming and error prone task with repeating procedures such as testing and verification. And even though there are several EDA tools which generate intellectual property (IP) blocks for specific purposes, to the best of our knowledge, there are no online tools able to design IP blocks from custom arithmetic functions. In this paper, we introduce our proof of concept (POC) circuit generator which is able to produce custom and verified hardware accelerators, specified in HDL, to speed up arbitrary integer arithmetic functions.