{"title":"用于OFDM应用的195K FFT/s(256点)高性能FFT/IFFT处理器","authors":"M. Vergara, M. Strum, W. Eberle, B. Gyselinckx","doi":"10.1109/ITS.1998.713131","DOIUrl":null,"url":null,"abstract":"A 256-point pipelined FFT/IFFT processor chip is described which implements OFDM modulation/demodulation functions. The architecture attains a sustained throughput of 195K FFT/s with incoming data rates of 100 MB/s. The 6.25 mm/sup 2/, 31300 gates chip was fully synthesized using 0.5 /spl mu/m, 3-layer metal CMOS process and operates at a frequency of 50 MHz.","PeriodicalId":205350,"journal":{"name":"ITS'98 Proceedings. SBT/IEEE International Telecommunications Symposium (Cat. No.98EX202)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 195K FFT/s (256-points) high performance FFT/IFFT processor for OFDM applications\",\"authors\":\"M. Vergara, M. Strum, W. Eberle, B. Gyselinckx\",\"doi\":\"10.1109/ITS.1998.713131\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 256-point pipelined FFT/IFFT processor chip is described which implements OFDM modulation/demodulation functions. The architecture attains a sustained throughput of 195K FFT/s with incoming data rates of 100 MB/s. The 6.25 mm/sup 2/, 31300 gates chip was fully synthesized using 0.5 /spl mu/m, 3-layer metal CMOS process and operates at a frequency of 50 MHz.\",\"PeriodicalId\":205350,\"journal\":{\"name\":\"ITS'98 Proceedings. SBT/IEEE International Telecommunications Symposium (Cat. No.98EX202)\",\"volume\":\"104 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ITS'98 Proceedings. SBT/IEEE International Telecommunications Symposium (Cat. No.98EX202)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITS.1998.713131\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ITS'98 Proceedings. SBT/IEEE International Telecommunications Symposium (Cat. No.98EX202)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITS.1998.713131","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 195K FFT/s (256-points) high performance FFT/IFFT processor for OFDM applications
A 256-point pipelined FFT/IFFT processor chip is described which implements OFDM modulation/demodulation functions. The architecture attains a sustained throughput of 195K FFT/s with incoming data rates of 100 MB/s. The 6.25 mm/sup 2/, 31300 gates chip was fully synthesized using 0.5 /spl mu/m, 3-layer metal CMOS process and operates at a frequency of 50 MHz.