Byung-Do Rhee, S. Min, Sung-Soo Lim, Heonshik Shin, Chong-Sang Kim, C. Park
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Issues of advanced architectural features in the design of a timing tool
This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach.<>