Constant time arbitrary length synchronous binary counters

The author introduces a synchronous binary counter which can be operated under a high clock frequency, independent of the counter's length n: all signals traverse at most two three-input logic gates during each clock phase. The proposed design is simple enough to have practical implications, as illustrated by a CMOS programmable gate array implementation which has counted up to 2/sup 40/ with a 40-MHz clock. The area required for laying out this design is no larger than that of the (much slower) carry-ripple counter.<>