{"title":"多核架构中具有父/子资源管理的异步双线程通信模块","authors":"Qingfei Xu, Xinyu Yang","doi":"10.1109/CICN.2016.115","DOIUrl":null,"url":null,"abstract":"While Multi-Core architecture has been widely applied to processor designing, the cross-domain communication is growing fast in this architecture and becomes a quite important method to estimate the processor performance. In this paper, we designed a novel communication mechanism that can be deployed as either message senders or receivers, proposed a dual-thread module which can help the communication processors quickly deal with the coming requests and implemented a parent/children resource management mechanism to effectively utilize the resources to improve their capacities of handling messages. We implemented this design on a FPGA platform with a three-core architecture installed ThreadX on each core of them, in the end we described the approach to evaluate our design which proved that this design can improve both resource utilization and communication performance.","PeriodicalId":189849,"journal":{"name":"2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Asynchronous Dual-Thread Communication Module with Parent/Children Resource Management in Multi-core Architecture\",\"authors\":\"Qingfei Xu, Xinyu Yang\",\"doi\":\"10.1109/CICN.2016.115\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"While Multi-Core architecture has been widely applied to processor designing, the cross-domain communication is growing fast in this architecture and becomes a quite important method to estimate the processor performance. In this paper, we designed a novel communication mechanism that can be deployed as either message senders or receivers, proposed a dual-thread module which can help the communication processors quickly deal with the coming requests and implemented a parent/children resource management mechanism to effectively utilize the resources to improve their capacities of handling messages. We implemented this design on a FPGA platform with a three-core architecture installed ThreadX on each core of them, in the end we described the approach to evaluate our design which proved that this design can improve both resource utilization and communication performance.\",\"PeriodicalId\":189849,\"journal\":{\"name\":\"2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICN.2016.115\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICN.2016.115","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Asynchronous Dual-Thread Communication Module with Parent/Children Resource Management in Multi-core Architecture
While Multi-Core architecture has been widely applied to processor designing, the cross-domain communication is growing fast in this architecture and becomes a quite important method to estimate the processor performance. In this paper, we designed a novel communication mechanism that can be deployed as either message senders or receivers, proposed a dual-thread module which can help the communication processors quickly deal with the coming requests and implemented a parent/children resource management mechanism to effectively utilize the resources to improve their capacities of handling messages. We implemented this design on a FPGA platform with a three-core architecture installed ThreadX on each core of them, in the end we described the approach to evaluate our design which proved that this design can improve both resource utilization and communication performance.