Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip

The cracking of the brittle ultra low-k dielectrics on advanced node silicon devices is a great concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effect. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer better electrical performance than solder, and better a capability of forming finer pitch joints than the solder bump reflow process [1, 2]. It is therefore important to understand the CPI challenges of Cu pillar on low k chip and device to overcome them. This paper reports our studies on the process development challenges when employing TCB-NCP processes on large size (18×18mm) low k chips which were processed by using GLOBALFOUNDRIES' 28nm technology node. Discussions include methods to minimize bond forces for large bonding areas and key underfill (NCP) BOM property selections to mitigate large die size and high bump counts induced by cold joints and low k stress are explored. Thermo-mechanical modeling and simulation to compare TCB-NCP vs. conventional C4 reflow + capillary underfill process on low k layer stress to assist in package BOM selection is also studied and reported.