{"title":"3.5-9.5 GHz紧凑型数字功率放大器，峰值PAE为39.3%，采用40nm CMOS技术","authors":"H. Qian, J. Liang, Xun Luo","doi":"10.1109/IEEE-IWS.2015.7164565","DOIUrl":null,"url":null,"abstract":"A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm2.","PeriodicalId":164534,"journal":{"name":"2015 IEEE International Wireless Symposium (IWS 2015)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 3.5–9.5 GHz compact digital power amplifier with 39.3% peak PAE in 40nm CMOS technology\",\"authors\":\"H. Qian, J. Liang, Xun Luo\",\"doi\":\"10.1109/IEEE-IWS.2015.7164565\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm2.\",\"PeriodicalId\":164534,\"journal\":{\"name\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEE-IWS.2015.7164565\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Wireless Symposium (IWS 2015)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2015.7164565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.5–9.5 GHz compact digital power amplifier with 39.3% peak PAE in 40nm CMOS technology
A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm2.
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