Physical Verification of Panel-Level Packaging Designs Utilizing Die Drift Patterning Technology

Panel-level packaging such as fan-out wafer-level packaging (FOWLP) has been a promising technology for a number of years now, primarily as a means of packaging semiconductor devices containing interconnect densities that exceed the capabilities of standard wafer-level chipscale packaging (WLCSP). One of the historical barriers to the broad adoption of panel-level packaging is the yield loss associated with “die drift”-die that shift from their designed nominal positions within each package during the manufacturing process. To break through this barrier, we introduce a novel die drift patterning technology that recognizes and adjusts for die drift, making “design during manufacturing” feasible and practical. However, both panel-level packaging and the die drift patterning methodology introduce physical verification challenges that are unfamiliar to most package designers. Panel-level packaging uses a GDSII or OASIS format for the package design, similar to integrated circuit (IC) design databases. Although design rule checking (DRC) is normally run on each individual unit GDSII file, the Die drift patterning process must also be simulated on a complete panel as one overall GDSII mask. This panel GDSII mask includes unique characteristics, with typically thousands of units requiring concurrent verification. The process is substantially more challenging than a classic unit design, where many repetitive GDSII cells exist within a hierarchy that can be used by the verification tools to improve runtimes. Deca collaborated with Mentor, a Siemens business (Mentor) to optimize physical verification for this panel GDSII mask verification. Together, they worked to identify operational impediments and implement optimizations to the verification toolsuite that enabled the platform to support verification of the die drift patterning technology for M-Series fan-out panel level packaging, while also achieving a reasonable turnaround time (TAT) for panel verification. This optimization utilizes both CPU scaling capabilities and a novel computational approach that accounts for the unique characteristics of a die drift patterning panel-level GDSII mask.