Component modeling for an integrated digital pixel

Future portable imaging products can benefit from the integration of a detector, analog-to-digital converter, digital processing, and data storage within a single chip. One approach combines these components into a processing element that can be tiled into a focal plane processor (FPP) array. Silicon area tradeoffs among the detector, analog interface, processing, and storage can influence system performance. This paper presents a technique that combines area models for each component of the tiled cell to evaluate system implementation alternatives for a 650mm/sup 2/ FPP array with Quad-CIF (176 /spl times/ 144) resolution. A pixel design tool enables comparisons of architectural design choices such as fill factor and data storage. Reducing data storage can increase fill factor. However, this sacrifices versatility in the application suite. Future work includes the development of performance models of each component based upon its physical implementation in silicon.