Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades

We can enhance the performance and efficiency of deflection-routed FPGA overlay NoCs by exploiting the cascading featureof the Xilinx UltraScale BlockRAMs. This allows us to (1) hardenthe multiplexers in the NoC switch crossbars, and (2) efficientlyadd buffering support to deflection-routing. While buffering isnot required for correct operation of a deflection routed NoC, it can boost network throughputs for large system sizes underheavy load and allow functional support for fixed-length, multi-flit NoC traffic. Since the multiplexer controls of the cascadedRAMs can be driven from user-logic, the NoC routing functioncan be implementing in LUTs while the data is steered acrossthe dedicated cascade multiplexers and links. Thus, our approachuses hard resources in the BlockRAM architecture to absorb thebulk of the cost of a NoC in the form of crossbar multiplexing, as well as packet queuing. For the XCVU9P UltraScale+ FPGA, we show how to map the 72b Hoplite NoC router at a cost of 3FIFO blocks, 64 LUTs, and 40 FFs per switch while operating at ≈727 MHz (400 MHz in 60×12 grid). This reduces LUT count by1.4× and FF cost by 2× over a pure LUT-based implementationwhile also being 1.2× faster. For uniform RANDOM traffic, weboost throughputs of a 16×16 NoC by 50–60%, reduce worst-case packet latency by ≈40%, and lower energy use by 10–40%over classic bufferless deflection-routing at injection rates of 15–20% and higher with 16-deep buffers. When compared to hardNoC router designs, our BRAM-based soft NoC also closes thearea gap to under a factor of two instead of the 20–23× gapclaimed in earlier studies.