{"title":"航天器用超高密度堆叠存储器海量数据记录仪","authors":"T. Sasada, S. Ichikawa, M. Shirakura","doi":"10.1109/AERO.2005.1559545","DOIUrl":null,"url":null,"abstract":"In 1999, Japan Aerospace Exploration Agency (JAXA) began developing a high-speed, large-volume and low-power-consumption solid state recorder (SSR) for space-use. This aim was to develop a SSR for installation in Earth observation satellites that could store and process large amounts of data. A prototype of the SSR was completed in spring 2004, and an engineering model is currently being constructed. The main features of the SSR are 200GBytes capacity, 2.5Gbps data transmission speed, low weight (25kg) and low power consumption (120W). Stacked 512Mbits synchronous dynamic random access memory (SDRAM) with on-board multi-bit error detection and correction (EDAC) mechanism, as well as a CompactPCI bus for fast data exchange, are used to improve the efficiency of data collection and storage capabilities. In this paper, we describe the main feature of the SSR system, and the technologies used in its development and manufacture. Preliminary results of several system tests are also reported","PeriodicalId":117223,"journal":{"name":"2005 IEEE Aerospace Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Mass Data Recorder with Ultra-High-Density Stacked Memory for Spacecraft\",\"authors\":\"T. Sasada, S. Ichikawa, M. Shirakura\",\"doi\":\"10.1109/AERO.2005.1559545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In 1999, Japan Aerospace Exploration Agency (JAXA) began developing a high-speed, large-volume and low-power-consumption solid state recorder (SSR) for space-use. This aim was to develop a SSR for installation in Earth observation satellites that could store and process large amounts of data. A prototype of the SSR was completed in spring 2004, and an engineering model is currently being constructed. The main features of the SSR are 200GBytes capacity, 2.5Gbps data transmission speed, low weight (25kg) and low power consumption (120W). Stacked 512Mbits synchronous dynamic random access memory (SDRAM) with on-board multi-bit error detection and correction (EDAC) mechanism, as well as a CompactPCI bus for fast data exchange, are used to improve the efficiency of data collection and storage capabilities. In this paper, we describe the main feature of the SSR system, and the technologies used in its development and manufacture. Preliminary results of several system tests are also reported\",\"PeriodicalId\":117223,\"journal\":{\"name\":\"2005 IEEE Aerospace Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Aerospace Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AERO.2005.1559545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Aerospace Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AERO.2005.1559545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mass Data Recorder with Ultra-High-Density Stacked Memory for Spacecraft
In 1999, Japan Aerospace Exploration Agency (JAXA) began developing a high-speed, large-volume and low-power-consumption solid state recorder (SSR) for space-use. This aim was to develop a SSR for installation in Earth observation satellites that could store and process large amounts of data. A prototype of the SSR was completed in spring 2004, and an engineering model is currently being constructed. The main features of the SSR are 200GBytes capacity, 2.5Gbps data transmission speed, low weight (25kg) and low power consumption (120W). Stacked 512Mbits synchronous dynamic random access memory (SDRAM) with on-board multi-bit error detection and correction (EDAC) mechanism, as well as a CompactPCI bus for fast data exchange, are used to improve the efficiency of data collection and storage capabilities. In this paper, we describe the main feature of the SSR system, and the technologies used in its development and manufacture. Preliminary results of several system tests are also reported