一种采用电容分离技术的浮栅mos低功耗CDMA匹配滤波器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221223

T. Yamasaki, T. Fukuda, T. Shibata

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引用次数: 11

摘要

基于浮栅MOS技术开发了低功耗、紧凑的CDMA匹配滤波器。采用单步匹配方案，并将匹配过程中不需要的耦合电容断开，实现了低功耗运行。以0.35-/spl mu/m工艺制作的255片匹配滤波器，在3v电源下工作6 mW，芯片速率为5 MS/S，芯片面积为1.0 mm/sup /。

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A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique

Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated 6 mW operation at 3 V power supply and the chip rate of 5 MS/S, while occupying the chip area of 1.0 mm/sup 2/.

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来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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