Improved error detection and correction for memory reliability against multiple cell upsets using DMC & PMC

The encroachment of technology grading — smaller dimensions, higher consolidation densities, and lower berth operating voltages — has come to a level that reliability of memory is put into jeopardy. Hence a novel approach is proposed to overcome this multiple cell upsets using error correction coding techniques. Recently, matrix computer code (MCs) based on senses of hamming codes have been proposed for computer storage protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. Decimal matrix coding (DMC) and Parity matrix coding (PMC) are the error correction coding techniques which are an extension of the matrix based hamming codes based on the divide symbol decimal algorithm with less overhead delay which will enhance the memory reliability. An error reuse technique (ERT) is used to reduce the area overhead without disturbing encoder and the decoder circuits. The proposed techniques i.e., Decimal matrix technique (DMC) and Parity matrix coding (PMC) are compared to well known present error correction coding techniques and the proposed techniques are compared among themselves for maximum error correction with complete detection.