MOS电流模式电路的突变短路和断路故障检测:一个案例研究

A. Madian, H. Amer, A. Eldesouky
{"title":"MOS电流模式电路的突变短路和断路故障检测:一个案例研究","authors":"A. Madian, H. Amer, A. Eldesouky","doi":"10.1109/BEC.2010.5631512","DOIUrl":null,"url":null,"abstract":"In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Catastrophic short and open fault detection in MOS current mode circuits: A case study\",\"authors\":\"A. Madian, H. Amer, A. Eldesouky\",\"doi\":\"10.1109/BEC.2010.5631512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.\",\"PeriodicalId\":228594,\"journal\":{\"name\":\"2010 12th Biennial Baltic Electronics Conference\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 12th Biennial Baltic Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BEC.2010.5631512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 12th Biennial Baltic Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BEC.2010.5631512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 22

摘要

本文讨论了模拟MOS电流模电路的灾难性断路和短路测试问题。讨论了一个基于6晶体管的晶体管电路的实例。假定每个晶体管有五故障模型,即任意两个端子之间的短路以及漏极或源极的开路。进行直流测试是为了降低测试成本,而不是需要昂贵设备的交流测试。假定在被测电路中只存在一个故障。采用MOSIS提供的0.18µm MOS模型进行了PSpice仿真。该电路在无故障状态下和每次注入单个故障后进行了仿真。对仿真结果进行了分析和比较。结果表明,总故障覆盖率为93%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Catastrophic short and open fault detection in MOS current mode circuits: A case study
In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信