{"title":"MOS电流模式电路的突变短路和断路故障检测:一个案例研究","authors":"A. Madian, H. Amer, A. Eldesouky","doi":"10.1109/BEC.2010.5631512","DOIUrl":null,"url":null,"abstract":"In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Catastrophic short and open fault detection in MOS current mode circuits: A case study\",\"authors\":\"A. Madian, H. Amer, A. Eldesouky\",\"doi\":\"10.1109/BEC.2010.5631512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.\",\"PeriodicalId\":228594,\"journal\":{\"name\":\"2010 12th Biennial Baltic Electronics Conference\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 12th Biennial Baltic Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BEC.2010.5631512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 12th Biennial Baltic Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BEC.2010.5631512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Catastrophic short and open fault detection in MOS current mode circuits: A case study
In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost instead of AC testing which requires expensive equipments. Only one fault is assumed to exist in the circuit under test. PSpice simulations have been carried out using the 0.18µm MOS model provided from MOSIS. The circuit has been simulated for fault-free condition and after injecting a single fault at a time into the circuit. The simulation results have been analyzed and compared. It is found that the total fault coverage is 93%.