Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications

In this paper, we investigate the potential of the hardware/software co-design to realize a flexible-low resources elliptic curve cryptography (ECC) processor over binary finite fields GF(2m) on FPGA platforms. A design is proposed that is capable to work over different curves recommended by the ECC standards, namely, m = 163, 283, 571 without reconfiguring either the software or the hardware. The proposed hardware-software co-design is hosted on a free-so ft-core processor from Xilinx FPGA, namely the PicoBlaze. Two novel arithmetic circuits that represent the hardware environment are introduced to perform multi-precision arithmetic and scalable reduction over GF(2m). Furthermore, the proposed architecture is parameterized for different data widths (8, 16, 32 bits) to evaluate the optimal resource utilization versus performance trade-off to be made for the low resource-end application while still maintaining flexibility (scalability) across the chosen curves. The implementation of the flexible ECC processor consumes only 392 (51%) and 534 (62%) slices of the lowest cost chips from Xilinx Spartan III namely XC3S50 for 8 and 16-bits data paths, and 1278 (66%) slices for 32-bit data path on Spartan III XC3S200.