Analysis and verification of hard tie-off signals of SoC

Nowadays MP-SoCs or embedded SoCs have several hundred thousands of hard tie-off signals. Mostly, hard tie-offs signals are verified or reviewed by SoC verification team along with SoC architecture team manually. It is very cumbersome and error prone process. Often, it becomes infeasible due to large number of hard tie-offs signal in SoC. It is one of the most challenging tasks in SoC verification. In this paper, we are proposing a verification methodology which automatically verifies hard tie-off signal values based on previous taped out SoC database(s), IP delivery database(s) and SoC Architecture Specification(for tie-off signals). For new IPs, we are proposing mutation based methodology for qualifying each tied signal. At the end, we are also proposing to generate one UVM sequence per IP basis for the verified hard tie signals. The proposed methodology was applied on SoC1/SoC4 [9] on final RTL design, we have found many critical logic bugs. We have seen this methodology improved productivity of hard tied verification by 10X or more in our UVM based SoC verification environments for three different SoCs. It improves the quality of verification.