{"title":"一种用于GA高清电视接收机的数字频锁集成电路的研制","authors":"Dong-Seog Han, Myeong-Hwan Lee, Kil-Houm Park","doi":"10.1109/icce.1997.625999","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed a n ASIC based on the new architecture. The developed ASIC has the gete count of 60K with a gate array technology that features on 0.5pm, 3.3V and 2metal-layers technology. The pull-in range of the proposed architecture is about k25OKHz with OdB carrier-to-noise ratio (CNR).","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Development Of A Digital FPLLl ASIC For GA HDTV Receivers\",\"authors\":\"Dong-Seog Han, Myeong-Hwan Lee, Kil-Houm Park\",\"doi\":\"10.1109/icce.1997.625999\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed a n ASIC based on the new architecture. The developed ASIC has the gete count of 60K with a gate array technology that features on 0.5pm, 3.3V and 2metal-layers technology. The pull-in range of the proposed architecture is about k25OKHz with OdB carrier-to-noise ratio (CNR).\",\"PeriodicalId\":127085,\"journal\":{\"name\":\"1997 International Conference on Consumer Electronics\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icce.1997.625999\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icce.1997.625999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Development Of A Digital FPLLl ASIC For GA HDTV Receivers
In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed a n ASIC based on the new architecture. The developed ASIC has the gete count of 60K with a gate array technology that features on 0.5pm, 3.3V and 2metal-layers technology. The pull-in range of the proposed architecture is about k25OKHz with OdB carrier-to-noise ratio (CNR).
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
