一个高性能断带隙基准的设计

2010 International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2010-07-18 DOI:10.1109/ICASID.2010.5551518

Jun Hu, Yongsheng Yin, Honghui Deng

{"title":"一个高性能断带隙基准的设计","authors":"Jun Hu, Yongsheng Yin, Honghui Deng","doi":"10.1109/ICASID.2010.5551518","DOIUrl":null,"url":null,"abstract":"A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Design of a high-performance brokaw band-gap reference\",\"authors\":\"Jun Hu, Yongsheng Yin, Honghui Deng\",\"doi\":\"10.1109/ICASID.2010.5551518\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1\",\"PeriodicalId\":391931,\"journal\":{\"name\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASID.2010.5551518\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551518","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

设计了一种高性能的CMOS带隙基准电路(BGR)。所提出的电路采用针对低电源电压应用优化的电流模式架构。电路的关键部分采用Brokaw BGR架构，采用三级运算放大器获得高PSRR，仅采用一阶温度补偿技术获得低温度系数。在1.8V工作电压下，该电路采用美国特许的0.18 μ m CMOS工艺，并给出了仿真结果。仿真结果表明，在- 40°C ~ 125°C温度范围内，温度系数为9 ppm/°K，电源电压从1.44V变化到2.16V时，参考电压波动在0.067m V以内。此外，在10khz时PSRR为108.5dB，功耗仅为0.355mW1

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design of a high-performance brokaw band-gap reference

A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 International Conference on Anti-Counterfeiting, Security and Identification

自引率

0.00%

发文量