现代微处理器的多位扰流漏洞分析

Athanasios Chatzidimitriou, G. Papadimitriou, Christos Gavanas, George Katsoridas, D. Gizopoulos
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引用次数: 13

摘要

集成电路的小型化在相同的硅面积上带来了更多的器件(因此更多功能),但也使它们更容易受到软(瞬态)错误的影响。在设计的早期阶段,对微处理器易受软错误影响的程度进行评估和理解,可以在硬件或软件层面引导明智、经济有效的保护决策。在最近的制造技术中,辐射(中子或其他粒子)对硅器件的影响明显更严重,并导致多比特扰动的数量增加。本文利用微架构级故障注入和完整的系统堆栈,分析了多比特扰动对现代微处理器的影响。我们详细介绍了在Gem5微架构模拟器上建模的ARM Cortex-A9 CPU的6个主要硬件组件上的多位扰动的影响,其中包括跨8个制造技术节点的15个工作负载。为了分析的目的,我们使用并扩展了GeFIN(基于gem5的故障注入器)框架来建模和分析CPU硬件结构中的多位故障。断层注入器的增强版本模拟了构造邻近区域的多位断层;现代硅芯片受辐射影响的一个非常现实的例子。我们的分析表明,在组件之间的单比特和三比特故障之间,架构脆弱性因子(AVF)从1.5倍(+50%)显著增加到3.2倍(+220%)。给出了各硬件结构和各技术节点在250nm ~ 22nm范围内的聚合多位AVF;我们的结果显示,单比特和聚合多比特测量值之间存在显著的AVF差异,随着技术节点的减少,AVF差异高达35%——这揭示了任何方法只考虑单比特误差时评估差距的大小。我们报告了整个ARM Cortex-A9 CPU跨技术节点的软错误失败率(FIT),我们的结果表明,在整个CPU FIT中,多比特故障的贡献在不同技术中持续增加,在22nm中达到21%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Multi-Bit Upsets Vulnerability Analysis of Modern Microprocessors
Miniaturization of integrated circuits brings more devices (thus more functionality) on the same silicon area but also makes them more vulnerable to soft (transient) errors. Assessment and understanding of the magnitude of a microprocessor's vulnerability to soft errors in early stages of the design can steer wise, cost-effective protection decision at the hardware or software level. In recent fabrication technologies, the effect of radiation (neutrons or other particles) is significantly more severe on silicon devices and leads to increased numbers of multi-bit upsets. In this paper, we analyze the effects of multi-bit upsets in modern microprocessors, using microarchitecture level fault injection and a complete system stack. We present details about the effects of multi-bit upsets on 6 major hardware components of an ARM Cortex-A9 CPU modeled on Gem5 microarchitectural simulator, with 15 workloads across 8 fabrication technology nodes. For the purposes of our analysis, we employ and extend the GeFIN (Gem5-based Fault INjector) framework to model and analyze multi-bit faults in the hardware structures of the CPU. The enhanced version of the fault injector models multi-bit faults in adjacent areas of a structure; a very realistic case when modern silicon chips are affected by radiation. Our analysis shows that the architectural vulnerability factor (AVF) significantly increases from 1.5x (+50%) to 3.2x (+220%) between single and triple-bit faults across components. We present the aggregate multi-bit AVF of each hardware structure and each technology node from 250nm to 22nm; our results show significant AVF difference between single bit and aggregate multi-bit measurements, up to 35% as the technology node decreases - this reveals the magnitude of the assessment gap when only single bit errors are considered by any method. We report soft error Failures in Time (FIT) rates for the entire ARM Cortex-A9 CPU across technology nodes and our results show that the contribution of multi-bit upsets in the overall CPU FIT consistently increases across technologies and reaches 21% in 22nm.
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