基于fll的5nm FINFET安全电路时钟故障检测器

Sanquan Song, S. Tell, B. Zimmer, Sudhir S. Kudva, N. Nedovic, C. T. Gray
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引用次数: 2

摘要

电子系统复杂性的快速增长增加了它们对黑客攻击的脆弱性,例如故障注入,包括通过定时错误在系统时钟中插入小故障来破坏内部状态。作为一种对策,本文提出了一种基于锁频环(FLL)的时钟故障检测器。由外部电源电压调节,该FLL锁定在系统时钟的16-36X,创建四个相位,通过在64-144X过采样来测量系统时钟。然后,这些样本用于检测频率并关闭锁频环,以及通过模式匹配检测故障。在5nm FINFET工艺中实现,它可以检测到输入40MHz时钟周期的3.125%的故障或脉宽变化,电源从0.5到1.0V不等。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
The rapid complexity growth of electronic systems nowadays increases their vulnerability to hacking, such as fault injection, including insertion of glitches into the system clock to corrupt internal state through timing errors. As a countermeasure, a frequency locked loop (FLL) based clock glitch detector is proposed in this paper. Regulated from an external supply voltage, this FLL locks at 16-36X of the system clock, creating four phases to measure the system clock by oversampling at 64-144X. The samples are then used to sense the frequency and close the frequency locked loop, as well as to detect glitches through pattern matching. Implemented in a 5nm FINFET process, it can detect the glitches or pulse width variations down to 3.125% of the input 40MHz clock cycle with the supply varying from 0.5 to 1.0V.
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