FPGA Implementation of a Novel Compensation Technique for EER Amplifiers

This paper examines a practical method to reduce the spectral distortion at the output of an Envelope Elimination and Restoration (EER) power amplifier (PA). The EER amplifiers utilized in terrestrial Amplitude Modulation (AM) radio broadcast transmitters are affected by non-linear and memory effects; the proposed compensation method exploits the source of these effects in real-world amplifiers. Specifically, using a new feed forward configuration for pre-processing the amplifier input, the algorithm predicts the PA output in real-time using its realistic behavior modeled through dynamic differential equations. The compensation method implemented at the base band considers the effects created by the most critical components of the EER amplifier, i.e, band-limiting of the envelope by the reconstruction filter and a non-linear load applied at the output of the reconstruction filter. The performance improvements of the proposed method are measured by its ability to reduce Total Harmonic Distortion (THD) at the output of the system. Taking advantage of the efficient utilization of available computational resources, the feasibility of implementing this system is verified using a FPGA platform.