Fractional-Order Image Edge Detector on FPGA

In this work, a Fractional-Order edge detector is designed and implemented. A floating point convolution unit is also presented exploiting hardware parallelism. The proposed design is suitable for both integer and fractional-order filters by exploiting the IEEE 754 floating point single precision representation. It also fits for different image resolutions. The design supports several tuning parameters for a greater degree of freedom in design, fractional-order parameter α, the filters used and the threshold. The system is implemented on VIRTEX 5 development board used. The maximum frequency achieved for 3×3 filter is 169.6 MHz.