用遗传算法自动生成顺序电路的测试图

Proceedings Eleventh International Conference on VLSI Design Pub Date : 1998-01-04 DOI:10.1109/ICVD.1998.646616

V. Rajesh, Ajai Jain

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引用次数: 8

摘要

本文讨论了一种利用遗传算法生成时序电路测试图的新目标函数。这种方法是基于为考虑中的错误分配一个值(0或1)的重要性。这是基于仿真的，可以用于任何可以逻辑模拟的电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Automatic test pattern generation for sequential circuits using genetic algorithms

This paper discusses a new objective function to generate test patterns for sequential circuits using genetic algorithms. This approach is based on the importance of assigning a value (0 or 1) to a line with respect to faults in consideration. This is simulation based and can be used for any circuit that can be simulated logically.

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Proceedings Eleventh International Conference on VLSI Design

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