Modelling of 6nm MOS and CMOS

A 6nm MOSFET and CMOS device presented in this paper. With 0.005v drain voltage a minimum channel length of 24nm and a optimized threshold voltage of 0.2360v is achieved in the present work. A 6nm n-type and p-type MOSFET is modelled and simulated to design CMOS device. The optimized device performance of the CMOS is presented. Indium Gallium Arsenide and Hafnium Oxide is used as semiconductor and oxide material. The electrical performance is evaluated in terms of supplied gate voltage $\mathrm{V}_{\mathrm{G}\mathrm{S}}$, Drain to Source Voltage $\mathrm{V}_{\text{DS}}$, Threshold Voltage $\mathrm{V}_{\mathrm{T}\mathrm{H}}$ and Drain Current ID. The 6nm gate length MOSFET device has achieved an optimized threshold voltage $(\mathrm{V}_{\mathrm{T}\mathrm{H}})$ 0.2360v drive current $(\mathrm{I}_{\mathrm{O}\mathrm{N}})$ of 19.152 ⨯ 10−5A/um, and leakage current $(\mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}})$ of 37.33 ⨯ 10−10 A/um.