Signal Integrity Analysis of High Speed Link Analog Front End Receiver for Cost Effective Packaging Schemes

In this paper, we have compared the signal quality at different points on the channel during high-speed data transmission in the Analog Front End Receiver (AFE) by analyzing the quality of eye diagrams in the presence of cost-effective packaging schemes. Simulation of Analog Front End Receiver developed in 28nm FD-SOI technology is performed with actual chip package S parameters at 1.25 Gb/s. The Simulation/Silicon Measurement results show that even a severely degraded eye diagram at the package balls does not result in a higher bit error rate. But actually, the quality of the eye diagram across the on-chip terminator resistor is the main parameter in achieving the required bit error rate specification.