一个快速流水线复杂乘法器:容错问题

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224347

L. Breveglieri, V. Piuri, D. Sciuto

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引用次数: 1

摘要

对串行复杂乘法专用器件进行了全面的讨论，包括结构、可靠性和容错性能。简要介绍了流水线体系结构。根据时钟速率、外部管路和管路填充度等几个指标进行了优化。利用图论方法分析了功能故障模型下的可测性特征，显示了设备的完全可测性。采用等差码的方法引入了错误检测，并对错误检测与成本之间的权衡进行了评估。最后通过第欧根尼方法引入了在线重构，并讨论了容错性和成本之间的权衡。讨论了基于解析插值软件仿真和CMOS技术中原型布局的评价。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A fast pipelined complex multiplier: the fault tolerance issues

A comprehensive discussion of a dedicated device for serial complex multiplication is presented, covering architectural, reliability and fault tolerance properties. The pipelined architecture is briefly described. It is optimized w.r.t. several figure of merits: clock rate, external pipelining and pipeline filling degree. Testability features are analyzed under functional fault models by means of graph-theoretic methods, showing full testability of the device. Error detection is introduced by means of arithmetic codes and the tradeoff between error detection and cost is evaluated. Eventually on-line reconfiguration is introduced through the Diogenes approach and the tradeoff between fault tolerance and cost is also discussed. Discussion are based on analytic interpolation software simulation and the evaluation of prototypal layouts in CMOS technology.<>

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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