基于65nm CMOS的6.3-8.7 GHz锁相环

Pizeng Zhou, Liang Wu, Chao Li, Zehui Kang, S. Zheng, Q. Xue
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引用次数: 0

摘要

本文提出了一种用于5G应用的全集成电荷泵锁相环(CPPLL)。锁相环由相位频率检测器(PFD)、电荷泵(CP)、低通滤波器(LPF)、压控振荡器(VCO)和可编程分压器组成。为了实现低相位噪声,压控振荡器采用c类拓扑结构。该锁相环采用65纳米CMOS实现,输出频率范围为6.3至8.7 GHz,相位噪声分别为-122.9 dBc/Hz和-116.6 dBc/Hz @1MHz。锁相环的功耗为50mw,除焊盘外,其核心面积为0.8 mm × 0.9 mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 6.3-8.7 GHz Phase-Locked Loop in 65nm CMOS
This paper presents a fully-integrated charge-pump phase-locked loop (CPPLL) for 5G applications. The PLL is composed of a phase and frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a programmable divider. To achieve low phase noise, the VCO employs class-C topology. Implemented in 65-nm CMOS, the PLL measures an output frequency range from 6.3 to 8.7 GHz, with phase noise of -122.9 dBc/Hz and -116.6 dBc/Hz @1MHz offset, respectively. The PLL consumes 50 mW and occupies a core area of 0.8 mm × 0.9 mm excluding the pads.
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