Enhancing dual-Vt design with consideration of on-chip temperature variation

dual-Vt technology is effective in leakage reduction and has been implemented in industry EDA tools. However, on-chip temperature is regarded as uniformly distributed over the chip, with a pre-assumed value. This assumption does not hold for designs in the deep sub-micron domain as on-chip temperature variation becomes more and more significant. As a result, treating temperature as a constant will either lead to non-optimal design in terms of leakage or unreliable circuit due to potential hot spots that have temperature higher than expected. In this paper, we propose a temperature-aware approach that leverages the on-chip temperature variation and takes into account the coupling effects between leakage and temperature to enhance the leakage reduction of any dual-Vt assignment algorithm. We synthesize and implement Opencore benchmarks using Synopsys tools and TSMC's 65nm low power dual-Vt library. The results show that we are able to improve the performance of a state-of-the-art dual Vt algorithm by an average of 11.2% in leakage saving, a more than 1.4°C drop of peak temperature, and a significant reduction of cells in hot regions without timing failure.