具有成本竞争力的PI-SI协同设计的DDR接口

K. Cai, S. Ji
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引用次数: 7

摘要

DDR片上交流输电总噪声可分解为高通滤波(HPF) Vppa和低通滤波(LPF) Vppb。PI-SI联合仿真表明,Vppa影响时序(眼宽),Vppb影响信号电压幅值(眼高),需要以不同的方式进行预算。因此,功率传输网络(PDN)经过优化,在保持可靠的SI性能的同时,以较小的外形尺寸显著降低了Cpkg和Cdie,这一点通过DDR接口进行了验证,并与特定SoC平台上的实验室测量数据相关联。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Cost competitive PI-SI co-design for DDR interfaces
The total DDR on-die AC power delivery noise can be decomposed into high pass filtered (HPF) Vppa and low pass filtered (LPF) Vppb. PI-SI co-simulation reveals that Vppa impacts timing (eye width) and Vppb impacts signal voltage amplitude (eye height), and they need to be budgeted in different manner. Consequently the Power Delivery Network (PDN) is optimized with significant Cpkg and Cdie reduction for a small form factor while maintaining the reliable SI performance, which is demonstrated with a DDR interface and correlated with lab measured data on a particular SoC platform.
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