Low Power Implementation of FBMC Transceiver for 5G Wireless Networks

Filter bank multi-carrier (FBMC) is the candidate modulation technique for the next generation of wireless networks (5G) as it provides a better spectral efficiency with little intersymbol interference (ISI) and intercarrier interference (ICI). Unfortunately, FBMC architecture has a complex structure; a large number of multipliers, adders, and subtractors are needed to implement fast fourier transform (FFT) and finite impulse response (FIR) components, which causes a high-power consumption and reduce the speed of the entire system especially in case of a large number of subscribers. This paper presents a complete design and implementation of a proposed low power FBMC transceiver architecture for a different number of multi-users or subscribers. The suggested method aims to reduce power consumption and area resources through reducing the complexity of the FFT (2n Points) processor by using a feedback loop with a (n) points FFT core. Also, the design of FIR filters is based on distributed arithmetic (DA) algorithm in which all multiplications and additions are replaced by a table and a shifter. The design and implementation are done using a Xilinx system generator tool and spartan-6 field programmable gate array (FPGA) board. The proposed implementation method presents a reduction in resources by 15 % compared to conventional implementation.