40纳米CMOS高分辨率高线性三步混合时间-数字转换器

2021 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM) Pub Date : 2021-11-28 DOI:10.1109/iWEM53379.2021.9790484

Biao Zhang, Xuefei Bai, Zhe Yang

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引用次数: 0

摘要

本文提出了一种基于40纳米CMOS技术的高分辨率、高线性度三步TDC设计。粗步是基于计数器设计的，以实现宽范围。为了提高系统的线性度，设计了基于DLL的多相时钟插补结构的中间步进。为了实现高分辨率，采用带环形振荡器的游标结构设计了精细步进。仿真结果表明，该设计具有5ps的分辨率和2 μs的范围。DNL为(−0.2,0.65)LSB, INL为(−0.9,0.38)LSB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A High-Resolution High-Linearity Three-Step Hybrid Time-to-Digital Converter in 40-nm CMOS

In this paper, a high-resolution high-linearity three-step TDC design in 40-nm CMOS technology is presented. The coarse step was designed based on a counter to achieve a wide range. The medium step was designed based on a multi-phase clock interpolation structure with DLL to improve the linearity. The fine step was designed based on a vernier structure with ring oscillators to achieve high resolution. The simulation results show that the design has a 5-ps resolution and a 2-μs range. The DNL is in (−0.2, 0.65) LSB, and the INL is in (−0.9, 0.38) LSB.

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2021 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM)

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