A simple testing structure for analog circuits

This paper presents a simple current-mode testing structure for analog circuit. The proposed structure is designed by the concept of the switch-current (SI) circuit. The proposed structure moderates the rigorous matching requirement and nonidealities induced by the conventional scan based testing structure. The proposed analog testing structure is divided into two operating modes that are self evaluation mode and built-in test mode. The loading phase and reading phase are both performed to complete the individual operating modes. As a result, the proposed testing structure itself can be evaluated in prior to the actual testing. This structure is digitally controlled and can be configured to accomplish a wider range of analog signal or verify more analog device under test (DUT). Simulation results also demonstrate the effectiveness of the proposed analog testing structure.