RTL Verilog处理器

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.238298

H. Jamal, S. Khan, F. Hameed, S. Saeed, M. Pasha

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摘要

本文提出了一种能够有效执行在寄存器传输层(RTL)编写的Verilog代码的处理器。它是一种RISC类型的处理器，执行Verilog HDL的多个过程块的并行执行。这将大大节省模拟时间。基于软件的仿真在普通奔腾处理器上的时钟周期的仿真时间是基于FPGA的处理器的仿真时间的百万倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An RTL Verilog processor

This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time. The simulation time taken by the software based simulation in terms of clock cycles on a normal Pentium Processor is Million times more than taken by this processor built on an FPGA.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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