两种故障-op/故障-op/故障安全架构的可靠性分析与比较

[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers Pub Date : 1989-06-21 DOI:10.1109/FTCS.1989.105637

Arun Kumar Somani, T. R. Sarnaik

{"title":"两种故障-op/故障-op/故障安全架构的可靠性分析与比较","authors":"Arun Kumar Somani, T. R. Sarnaik","doi":"10.1109/FTCS.1989.105637","DOIUrl":null,"url":null,"abstract":"Two different fault-tolerant architectural concepts for a computer node to be used in a distributed embedded environment have been developed to meet the requirements that the system can sustain at least two independent, nonsimulation hardware failures and remain operational. The architectures are distinguished by the organization of their fault-tolerant algorithm hardware. An analysis is made of these two architectures, and several issues on the reliability analysis of such complex architectures are addressed. Techniques are developed to reduce the complexity of the reliability model. An analysis of the interrelationship between the number of retries and their effect upon system reliability for different average transient lifetimes has also been performed.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Reliability analysis and comparison of two fail-op/fail-op/fail-safe architectures\",\"authors\":\"Arun Kumar Somani, T. R. Sarnaik\",\"doi\":\"10.1109/FTCS.1989.105637\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two different fault-tolerant architectural concepts for a computer node to be used in a distributed embedded environment have been developed to meet the requirements that the system can sustain at least two independent, nonsimulation hardware failures and remain operational. The architectures are distinguished by the organization of their fault-tolerant algorithm hardware. An analysis is made of these two architectures, and several issues on the reliability analysis of such complex architectures are addressed. Techniques are developed to reduce the complexity of the reliability model. An analysis of the interrelationship between the number of retries and their effect upon system reliability for different average transient lifetimes has also been performed.<<ETX>>\",\"PeriodicalId\":230363,\"journal\":{\"name\":\"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FTCS.1989.105637\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTCS.1989.105637","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

针对分布式嵌入式环境中使用的计算机节点，提出了两种不同的容错体系结构概念，以满足系统能够承受至少两个独立的非仿真硬件故障并保持运行的要求。这些体系结构是通过容错算法硬件的组织来区分的。对这两种结构进行了分析，并对这类复杂结构的可靠性分析问题进行了探讨。开发了降低可靠性模型复杂性的技术。本文还分析了不同平均暂态寿命下重试次数与重试次数对系统可靠性的影响之间的相互关系。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reliability analysis and comparison of two fail-op/fail-op/fail-safe architectures

Two different fault-tolerant architectural concepts for a computer node to be used in a distributed embedded environment have been developed to meet the requirements that the system can sustain at least two independent, nonsimulation hardware failures and remain operational. The architectures are distinguished by the organization of their fault-tolerant algorithm hardware. An analysis is made of these two architectures, and several issues on the reliability analysis of such complex architectures are addressed. Techniques are developed to reduce the complexity of the reliability model. An analysis of the interrelationship between the number of retries and their effect upon system reliability for different average transient lifetimes has also been performed.<>

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来源期刊

[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers

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