Control design and frequency analysis of an output filter in parallel interleaved converters

An important characteristic in multicell parallel voltage source converters (VSCs), besides the enhancing of the current capacity, is the possibility of decreasing the energy storage in the output filter by interleaving the pulses sent to the semiconductors. As consequences, the filter components are smaller, losses are reduced and the electrical dynamics is enhanced, i.e. the filter presents higher bandwidth. Despite the higher speed as the number of cells increases, the filter's closed loop dynamics cannot follow continuously this improvement once the sampling/switching frequency limits the controller actuation. This paper presents a review about VSC output LCL filters and describes a methodology for the current controller design followed by an analysis in the frequency domain of the system's overall dynamics as the number of cells increases.