利用SysML和simulink模型协同仿真验证嵌入式系统规范

R. Kawahara, Dolev Dotan, T. Sakairi, A. Kirshin, T. Sakairi, A. Kirshin, K. Ono, H. Ishikawa
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引用次数: 55

摘要

作者提出了对SysML的扩展,使其能够描述连续时间行为。利用SysML和MATLAB / Simulink的联合仿真,开发了集成在eclipse平台上的执行工具。为了证明该工具和SysML扩展在验证嵌入式系统规范方面的有效性,我们创建了一个示例模型,并通过在测试用例下检查约束来分析其执行结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Verification of embedded system's specification using collaborative simulation of SysML and simulink models
The authors propose an extension of SysML which enables description of continuous-time behavior. The authors also develop its execution tool integrated on Eclipse-based platform by exploiting co-simulation of SysML and MATLAB / Simulink. To demonstrate the effectiveness of the tool and the extension to SysML in verifying specifications of an embedded system, we create a sample model and analyze its execution results by checking constraints under a test case.
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