{"title":"在新型并行DSP架构上实现复杂FIR滤波器","authors":"A. Grigore, Radu Pralea, A. Enescu","doi":"10.1109/ISSCS.2013.6651182","DOIUrl":null,"url":null,"abstract":"The current paper describes a novel high-parallel architecture of a DSP (Digital Signal Processing) core and depicts optimizing techniques for implementation using the affiliated compiler. A demonstrative benchmark is presented for a FIR (Finite Impulse Response) complex filter, emphasizing differences over known digital signal processors.","PeriodicalId":260263,"journal":{"name":"International Symposium on Signals, Circuits and Systems ISSCS2013","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementing a complex FIR filter on a novel parallel DSP architecture\",\"authors\":\"A. Grigore, Radu Pralea, A. Enescu\",\"doi\":\"10.1109/ISSCS.2013.6651182\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The current paper describes a novel high-parallel architecture of a DSP (Digital Signal Processing) core and depicts optimizing techniques for implementation using the affiliated compiler. A demonstrative benchmark is presented for a FIR (Finite Impulse Response) complex filter, emphasizing differences over known digital signal processors.\",\"PeriodicalId\":260263,\"journal\":{\"name\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCS.2013.6651182\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Signals, Circuits and Systems ISSCS2013","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2013.6651182","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementing a complex FIR filter on a novel parallel DSP architecture
The current paper describes a novel high-parallel architecture of a DSP (Digital Signal Processing) core and depicts optimizing techniques for implementation using the affiliated compiler. A demonstrative benchmark is presented for a FIR (Finite Impulse Response) complex filter, emphasizing differences over known digital signal processors.
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