基于45 nm PD-SOI CMOS的60ghz 30.5% PAE二阶谐波差分叠加放大器

2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2019-01-01 DOI:10.1109/SIRF.2019.8709143

Radu Ciocovean, R. Weigel, A. Hagelauer, V. Issakov

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引用次数: 4

摘要

提出了一种具有二次谐波控制的60 GHz高效单级差分堆叠AB类功率放大器。该电路采用45纳米PD-SOI CMOS技术实现。测量结果表明，该功率放大器在60 GHz时的最大输出功率($P_{max}$)为15.3 dBm，竞争最大功率附加效率($PAE_{max}$)为30.5%。输出参考的1db压缩点(OP1dB)为9.5 dBm。此外，该电路从1.8 V电源中吸取40mA，芯片核心尺寸为0。36 mmx0.35毫米。

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A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS

This paper presents a 60 GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power ($P_{max}$) of 15.3 dBm with a competitive maximum power-added efficiency ($PAE_{max}$) of 30.5 % at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8 V supply and the chip core size is 0. 36mmx0.35 mm.

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2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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