Iterative parallel shift sort : Optimization and design for area constrained applications

Sorting is an important computational task needed in almost all the modern data processing applications. Insertion sort is one of the simplest algorithms used for sorting. However, implementation of insertion sort in sequential execution leads to a time complexity O(n2) making it less efficient. This often leads to not preferring this sorting algorithm for many applications. This paper explores the insertion sort implementation in VHDL using parallel shift sort technique which results in linear time complexity O(n). The designed model is further optimized for operation at higher data rates. An iterative design using the optimized model is then implemented on Xilinx Spartan-6 FPGA which uses in-place computations and allows processing of large data with less hardware resources. This makes the iterative design ideal for area constrained applications which operate in a dynamic input environment with fixed hardware such as real time sensor data processing.