双极自启动多发射极BiCMOS (B/sup 2/M-BiCMOS)逻辑低压应用

Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI:10.1109/ICECS.1996.584632

Chung-Yu Wu, Yuh-Kuang Tseng

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引用次数: 1

摘要

提出并分析了一种新的全摆幅BiCMOS逻辑电路——自举式多发射极BiCMOS (B/sup /M-BiCMOS)逻辑。在1 /spl mu/m技术下，采用HSPICE仿真比较了新型BiCMOS逻辑电路与CMOS、传统BiCMOS和自举BiCMOS (BS-BiCMOS)逻辑电路的速度性能。结果表明，与BS-BiCMOS (CMOS)逻辑门相比，具有2 V电源电压和0.5 pF输出负载的新型B/sup 2/M-BiCMOS 3输入NAND门的传输延迟时间提高了36%(72%)，而B/sup 2/M-BiCMOS 5输入和7输入NAND门的传输延迟时间分别提高了1.84(2.4)倍和2.16(3.1)倍。这种优越的性能使得B/sup /M-BiCMOS在许多低压BiCMOS应用中都是可行的。

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Bipolar bootstrapped multi-emitter BiCMOS (B/sup 2/M-BiCMOS) logic for low-voltage applications

A new full-swing BiCMOS logic circuits called the bootstrapped multi-emitter BiCMOS (B/sup 2/M-BiCMOS) logic is proposed and analyzed. HSPICE simulations have been performed to compare speed performance of the new BiCMOS logic circuit with those of CMOS, conventional BiCMOS, and Bootstrapped BiCMOS (BS-BiCMOS) logic circuits, in 1 /spl mu/m technology. It has been shown that as compared to BS-BiCMOS (CMOS) logic gate, the new B/sup 2/M-BiCMOS 3-input NAND gate with 2 V supply voltage and 0.5 pF output loading has about 36% (72%) improvement in the propagation delay time whereas the B/sup 2/M-BiCMOS 5- and 7-input NAND gates have 1.84 (2.4) and 2.16 (3.1) times of improvement, respectively. This advantageous performance makes the B/sup 2/M-BiCMOS feasible in many low-voltage BiCMOS applications.

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Proceedings of Third International Conference on Electronics, Circuits, and Systems

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