SiO/sub x/N/sub y/ Ta/sub 2/O/sub 5/堆叠栅氧化物在应变si上的电学特性

Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003 Pub Date : 2003-07-07 DOI:10.1109/IPFA.2003.1222755

C. Maiti, S. Samanta, G. Dalapati, S. Chatterjee

{"title":"SiO/sub x/N/sub y/ Ta/sub 2/O/sub 5/堆叠栅氧化物在应变si上的电学特性","authors":"C. Maiti, S. Samanta, G. Dalapati, S. Chatterjee","doi":"10.1109/IPFA.2003.1222755","DOIUrl":null,"url":null,"abstract":"In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Electrical characterization of SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ stacked gate oxides on strained-Si\",\"authors\":\"C. Maiti, S. Samanta, G. Dalapati, S. Chatterjee\",\"doi\":\"10.1109/IPFA.2003.1222755\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.\",\"PeriodicalId\":266326,\"journal\":{\"name\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2003.1222755\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2003.1222755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在本文中，我们研究了SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/栅极堆叠作为未来应变si CMOS应用的可能候选者，并展示了高k栅极介质与应变si集成的可能性。

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Electrical characterization of SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ stacked gate oxides on strained-Si

In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.

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Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003

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