可靠的cmp片上存储器设计

Abbas BanaiyanMofrad
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引用次数: 1

摘要

在深亚微米范围内的激进技术缩放使芯片更容易发生故障。这给现代芯片的设计带来了多重可靠性挑战,包括制造缺陷、损耗和参数变化。随着芯片多处理器(cmp)等现代计算平台中不同的片上存储器所占的空间越来越大,存储器的可靠性成为一个具有挑战性的问题。传统的片上存储器可靠性技术(例如,ECC)会产生显著的功耗和性能开销。为了应对这些挑战,我的研究介绍了单核处理器[1]中L1和L2缓存存储器的容错设计,cmp[3][4]中的最后一级缓存(LLC),以及片上网络(noc)[2]中的LLC。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reliable On-Chip Memory Design for CMPs
Aggressive technology scaling in deep sub micron regime makes chips more susceptible to failures. This causes multiple realibility challenges in the design of modern chips, including manufacturing defects, wear-out, and parametric variations. With increasing area occupied by different on-chip memories in modern computing platforms such as Chip Multi-Processors (CMPs), memory reliability becomes a challenging issue. Traditional on-chip memory reliability techniques (e.g., ECC) incur significant power and performance overheads. To tackle such challenges, my research introduces several designs for fault-tolerance of both L1 and L2 cache memories in uni-core processors [1], Last-level Cache (LLC) in CMPs [3][4], and LLC in Networks-on-Chip (NoCs) [2].
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