Performance evaluation of Network on Chip architectures

A new chip design paradigm Network on Chip (NOC), proposed by many research groups [1], [2] is an important architectural choice for future SOCs. Various proposed Network on Chip (NoC) architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques, some of the topologies are CLICHE, Folded Torus, BFT, SPIN and Octagon. This research work compares proposed NoC architectures and to evaluate their performance using a simulating tool NS-2. Simulation provides relationship among latency, throughput and packet drop probability for NoC architectures.