最大李雅普诺夫指数的硬件实现

2013 Fourth Argentine Symposium and Conference on Embedded Systems (SASE/CASE) Pub Date : 2013-10-21 DOI:10.1109/SASE-CASE.2013.6636776

L. De Micco, M. Antonelli, C. Gonzalez, H. Larrondo

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引用次数: 2

摘要

本文利用现场可编程门阵列(FPGA)设计并实现了一个最大李雅普诺夫指数(MLE)量化器的硬件实现。该设计在精度方面进行了优化，采用浮点结构来表示值。该设计充分利用了MLE计算方程的并行性，并允许基于FPGA技术的并行实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware implementation of maximum Lyapunov exponent

In this paper a hardware implementation of a Maximum Lyapunov Exponent (MLE) quantifier is designed and implemented using a field programmable gate array (FPGA). The design was optimized in terms of accuracy employing floating point architecture to represent the values. The proposed design takes advantage of the underline parallelism of the MLE computation equations and allows its concurrent implementation based on FPGA technology.

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2013 Fourth Argentine Symposium and Conference on Embedded Systems (SASE/CASE)

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