基于锁相环的无参考CDR研究

2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI:10.1109/ISOCC.2016.7799779

Jihoon Kim, Y. Hwang, Yong Moon

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引用次数: 3

摘要

时钟数据恢复(CDR)电路是串行数据通信的重要组成部分。S/PDIF是一种数据编码。基于锁相环的CDR可恢复2.8224 ~ 24.576MHz的时钟和数据，并设计了频率检测器(FD)，利用前置电路检测频率。利用锁相环、频率检测器(FD)和复位电路设计了基于锁相环的无参考CDR。本研究采用65nm CMOS工艺。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A study of the referenceless CDR based on PLL

Clock data recovery (CDR) circuit is an essential component for serial data communication. S/PDIF which is one of data coding is used. The CDR based on PLL recovers clock and data of 2.8224 ~ 24.576MHz and was designed with the frequency detector (FD) to detect the frequency by using the preamble. The PLL, frequency detector (FD) and the reset circuits were used to design the refernceless CDR based on PLL. 65nm CMOS process is used in this study.

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2016 International SoC Design Conference (ISOCC)

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