{"title":"全集成CMOS DC-DC转换器的优化问题","authors":"S. Musunuri, P. Chapman","doi":"10.1109/IAS.2002.1042782","DOIUrl":null,"url":null,"abstract":"A general approach is given for minimizing the chip area occupied by fully integrated CMOS continuous mode buck and boost converters. It is shown that most significant portion of the area is occupied by the planar inductors. It is also shown that in most cases, continuous conduction mode requires that the minimum (critical) inductance must be used to minimize area. A design example accompanies the analysis, along with experimental results from a test integrated circuit.","PeriodicalId":202482,"journal":{"name":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Optimization issues for fully-integrated CMOS DC-DC converters\",\"authors\":\"S. Musunuri, P. Chapman\",\"doi\":\"10.1109/IAS.2002.1042782\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A general approach is given for minimizing the chip area occupied by fully integrated CMOS continuous mode buck and boost converters. It is shown that most significant portion of the area is occupied by the planar inductors. It is also shown that in most cases, continuous conduction mode requires that the minimum (critical) inductance must be used to minimize area. A design example accompanies the analysis, along with experimental results from a test integrated circuit.\",\"PeriodicalId\":202482,\"journal\":{\"name\":\"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IAS.2002.1042782\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAS.2002.1042782","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization issues for fully-integrated CMOS DC-DC converters
A general approach is given for minimizing the chip area occupied by fully integrated CMOS continuous mode buck and boost converters. It is shown that most significant portion of the area is occupied by the planar inductors. It is also shown that in most cases, continuous conduction mode requires that the minimum (critical) inductance must be used to minimize area. A design example accompanies the analysis, along with experimental results from a test integrated circuit.