{"title":"用于基站应用的多标准信道解码器","authors":"Timo Vogt, N. Wehn, P. Alves","doi":"10.1145/1016568.1016621","DOIUrl":null,"url":null,"abstract":"In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs. The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A multi-standard channel-decoder for base-station applications\",\"authors\":\"Timo Vogt, N. Wehn, P. Alves\",\"doi\":\"10.1145/1016568.1016621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs. The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.\",\"PeriodicalId\":275811,\"journal\":{\"name\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1016568.1016621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1016568.1016621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-standard channel-decoder for base-station applications
In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs. The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.