简化IEEE 1284软IP设计，实现系统集成电路

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824081

Jung-Han Lee, Dong-Wook Kim, W. Cho

{"title":"简化IEEE 1284软IP设计，实现系统集成电路","authors":"Jung-Han Lee, Dong-Wook Kim, W. Cho","doi":"10.1109/APASIC.1999.824081","DOIUrl":null,"url":null,"abstract":"The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reduced IEEE 1284 soft IP design for system IC implementation\",\"authors\":\"Jung-Han Lee, Dong-Wook Kim, W. Cho\",\"doi\":\"10.1109/APASIC.1999.824081\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824081\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824081","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

作者提出了一种用于系统集成电路实现的IEEE 1284软IP。他们设计了一种减少高速和小栅极计数的模式。设计的IP可以作为系统集成电路使用。通过仿真，作者在实际系统集成电路设计过程中验证了所设计的IP适用于特定的工艺技术。最后，他们考虑了哪种形式的IP可以有效地用于系统集成电路设计的算法级。

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Reduced IEEE 1284 soft IP design for system IC implementation

The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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